The physical layout of a VLSI design has to adhere to certain design constraints which may be dictated mostly by the technology used to fabricate the design to ensure manufacturability. As the industry has moved towards denser chips with smaller features and nodes, the number of constraints and the attendant complexities have increased. For example, there are more than a thousand such constraints that may be applicable to a design for the current 20 nm regime. With this increase, there is a need for a comprehensive display of design rule violations within a layout such that designers can efficiently understand and solve the violations.